One or more embodiments of the present invention relate to the field of digital computer systems, and more specifically, to a method for securing operation of an integrated circuit (IC) device.
Specific hardware designs are required to create trust in a computing system where it is important to maintain the confidentiality and integrity of the information; in particular, when the information is digitally signed.
Cryptographic accelerators are becoming more prevalent on processors and multi-chip platforms. They offer digital signature/sign capabilities. Thousands of signatures per second are achievable on current hardware engines. Such systems require a steady background traffic consisting of such signatures. However this requirement is negligible in terms of capacity. The signing traffic requires human-scale latencies between devices which are many orders of magnitude below that of local interconnect latencies.